Define physical address and logical address. New 8086 microprocessor. converts a logical address into physical address? Explain with example.

Subject Microprocessor and Assembly Language
NU Year Set: 2.(a) Marks: 6 Year: 2010

Address generated by CPU while a program is running is referred as Logical Address. The logical address is virtual as it does not exist physically. Hence, it is also called as Virtual Address. This address is used as a reference to access the physical memory location. The set of all logical addresses generated by a programs perspective is called Logical Address Space.

Physical Address identifies a physical location in a memory. MMU (Memory-Management Unit) computes the physical address for the corresponding logical address. MMU also uses logical address computing physical address. The user never deals with the physical address. Instead, the physical address is accessed by its corresponding logical address by the user. The user program generates the logical address and thinks that the program is running in this logical address. But the program needs physical memory for its execution. Hence, the logical address must be mapped to the physical address before they are used.

In a paging system, the process’ space is divided into consecutive pages of fixed length:
Page 0, Page 1, Page 2, etc.
As such, a logical address (also called a virtual address) consists of:
A page number
An offset within that page
In a paging system, main memory is divided into consecutive frames of fixed length (same
length as the pages):
Frame 0, Frame 1, Frame 2, etc.
Some of the logical pages are placed in the physical frames. For example, pages 3, 8 and 10
might be placed in frames 104, 87 and 378, respectively, with the other pages of the process in
virtual memory, i.e., on disk (or other form of secondary memory).
The goal of this exercise is to help you understand 4 approaches to converting a logical address
(page number + offset) to a physical address (frame number + offset, or a page fault if the page
is not in main memory):
Simple indexing
Multi-level indexing
Hashing into an inverted page table
Associative lookup in a cache called the translation lookaside buffer (TLB)
Real operating systems will often use a combination of these 4 approaches. In addition, there is
an interaction with the main memory cache (see Figure 8.10 in your text).
Throughout this exercise, logical addresses and physical addresses are written as pairs of
numbers (page number offset for logical addresses, frame number/offset for physical addresses).
These are physically manifested as the high and low bits of a binary number.

Login to post your comment.